logic gate
英 [ˈlɒdʒɪk ɡeɪt]
美 [ˈlɑːdʒɪk ɡeɪt]
n. 逻辑门，逻辑闸(以两种方式之一对所输入数据进行输出的电子开关)
牛津词典
noun
- 逻辑门，逻辑闸（以两种方式之一对所输入数据进行输出的电子开关）
an electronic switch that reacts in one of two ways to data that is put into it. A computer performs operations by passing data through a very large number of logic gates .
英英释义
noun
- a computer circuit with several inputs but only one output that can be activated by particular combinations of inputs
双语例句
- This paper discusses the classification of logical functions, and proposes a tabular method to realize an arbitrary three-variable function by using NP type three-variable universal logic gate f4, and gives out several design examples.
本文讨论了逻辑函数的分类，提出了使用NP型三变量通用逻辑门f4实现任意三变量函数的查表方法，并给出了设计实例。 - Within this context, the first chapter indicates quantum logic gate and the second chapter demonstrates composing and running of the quantum C-NOT gate.
本文第一章介绍了量子逻辑门，第二章介绍了量子C-NOT门的构成及运行，第三章和第四章是具体的研究工作。 - This thesis focuses on the potential applications of memristor in chaotic circuit and logic gate structure.
本文着重研究忆阻器在混沌电路和逻辑门电路构造中的应用潜力。 - This paper introduces a new structure of numeral multilier: using one-level logic gate structure to realize array numeral multiplier, and using cmos technology to realize 8 × 8 ultraspeed array numeral multiplier with a new structure.
本文介绍了一种新的数码乘法器结构：采用一级逻辑门结构实现阵列式数码乘法器，并采用CMOS工艺技术实现新结构的8×8位超高速阵列式数码乘法器。 - Based on the I-U characteristics of single-electron transistor ( SET) and the concepts of CMOS digital circuits design, a sort of logic gate is proposed.
基于单电子晶体管（SET）的I＿U特性和CMOS数字电路设计思想，提出了一类互补型SET逻辑门。 - Based on the dual-rail logic, a cascadable parallel binary logic gate was, proposed.
基于双轨逻辑，本文提出一种可级联的并行二值逻辑门。 - And a computer inside actually assembles with many digital circuits, while digital circuits can be seen as the logic gate network that achieve by the electronic devices.
而一台电子计算机的内部实际上是由许许多多个数字电路组成，而数字电路可以看作是用电子器件实现的逻辑门网络。 - It is useful for quantum logic gate and quantum computer memory.
该编码既适用于量子逻辑门的防错和纠错，也适用于防止量子计算机存储单元的解相干。 - Josephson junction logic gate
约瑟夫逊结逻辑门电路 - This paper presents the conversion from dynamic logic gate to Markov chain, the solution of dynamic subtree top event failure probability and the method of obtaining the failure mode of subsystem using Markov model, that is sequence cutsets of the dynamic subtree.
论文研究了动态逻辑门向马尔可夫链的转化方法，利用马尔可夫链法求解动态子树顶事件概率，以及通过马尔可夫状态转移图直接找出子系统的故障模式和薄弱环节，即得到动态子树的顺序割集。